PN (p-type abutting n-type) semiconductor junctions are ubiquitous in the industry and play a principal role in electronic devices such as Diodes, Silicon-Controlled Rectifiers, Thyristors, Bipolar Junction Transistors (BJTs), Junction Field Effect Transistors (JFETs), and in optoelectronic devices such as Light-Emitting Diodes (LEDs) and Vertical Cavity Surface-Emitting Lasers (VCSELs). Electronic circuits that activate (‘drive’) the PN junctions are also common in the art and vary from resistor-divider circuits employed for BJT-based circuits to current-pulse circuits employed where only a transient activation of the junction is required. PN junctions display a ‘rectifying’ property, conducting electric current in one direction and blocking it in the opposite direction. In transistors, the PN junction labeled the ‘base’ in BJTs or the ‘gate’ in JFETs functions as the control location that regulates current flow through the device.
Activating the PN junction that functions as the control input for BJT's or JFETs often requires the flow of static current through the junction. For example, a BJT device employed to regulate the current flow through an electronic circuit will allow a current to pass through it that is a multiple of the device current gain, β and the current flowing into the base PN junction. Another example is that of an ‘enhancement-mode’, normally-off JFET device wherein a conduction channel is formed by the injection of a current into it's gate PN junction.
Other types of transistor devices exist wherein a static current flow into the control-input is not required for the operation of the devices. Examples of such devices are MOSFET and ‘depletion-mode’ JFET devices. Static current flow into the control input of a transistor device is, in some applications, an undesirable characteristic of the circuit and an unwanted expenditure of energy. Nevertheless, the principal characteristics of devices requiring control-input current, such as current-gain, low output resistance, speed of operation, simplicity and low-cost nature of manufacture etc., may prove to be attractive enough for their use despite the burden of the control-input current. It is desired in such cases that the energy expended due to the control-input current (in PN junction base or gate drive) be minimized in order to improve overall operational efficiencies and to minimize cost. Alternately, it may be desired that a facility to vary the control-input current is made available, that incurs minimal additional energy expenditure, and that does not depend upon external components.
In certain applications, minimizing the energy loss due to the gate drive current is critical to the quality of the solution. An example is the use of enhancement-mode or depletion-mode JFET switches in DC-to-DC conversion applications, a technology currently in the commercialization phase [1]. Of specific relevance is a class of converters called ‘buck’ DC-to-DC converters. These converters transform an input voltage into a lower output voltage through the use of switches that convey the input voltage, pulse-width modulated, into an energy-storing output filter. Common examples of the use of such converters are microprocessor power supplies. Maintaining high efficiencies in power supply voltage conversion is critical in such applications due to the costs associated with managing thermal dissipation within the system. The use of enhancement-mode JFET switches in buck conversion results in additional energy expense (as compared with MOSFET switches) due to the static drive current requirement. Certain JFET devices [1] may require as much as 40 mA of gate drive to cause the ON resistance of the device to reduce to 4.5 milliohms with the device conducting 10 A of current. With the control input driver circuit operating from a 5V supply, the static power consumption is 200 milliwatts, while the power consumption in the device channel due to current flow is 450 milliwatts. Assuming a 1V output from the buck converter, and a 20% 5V input duty cycle (or an 80% duty cycle for a switch device on the ground-side of the converter) in a 5V to 1V conversion, this drive power into the switch device alone is seen to contribute to a reduction in efficiency of 1.6%. In systems requiring extremely high conversion efficiency, such as battery operated computing devices, or thermally constrained systems, this loss in efficiency makes the JFET-based solution unattractive.
FIG. 1 illustrates the prior art interconnection of a driver circuit and the control input of a PN-junction gated device such as a BJT or a power-JFET. The interconnection of interest is the signal labeled ‘drive’ emanating from the driver circuits through the parallel combination of the resistance R and the capacitance C into the control input of the switch device labeled LS (for low-side). In this prior art drive circuit, resistance R limits the current flow into device LS and capacitance C enables faster turn-on and turn-off as well as in maintaining the device LS in it's ‘off’ state. For example, when the driver circuits determine that device LS is to be turned off, signal drive is brought down to ground from its high value (typically the value of power input VDRV). This negative transition in voltage couples through capacitance C into the input capacitance of device LS and produces a negative bias at this input node. But the presence of resistance R complicates matters in this prior art implementation by decaying this negative charge deposited at the input node of LS back into the signal drive, which is now at the ground potential. This decay is detrimental in systems employing JFETs because such JFETs may need a constant negative bias at their control gate to maintain the device in its ‘off’ or non-conducting state. This places a lower limit on the operating frequency of the switching conversion system. But because systems may desire to reduce the operating frequency to reduce C·V2·f losses in conditions of lower power consumption, this constraint is undesirable. Also, devices R and C are external components, and because of their large values, may not allow integration into the driver.
The invention specifies an innovative circuit architecture that successfully addresses the problems discussed above.